This invention relates to the manufacture of complimentary insulated gate metal oxide on silicon (CMOS) integrated circuits and more particularly to an improved method of obtaining desired edge profiles in contact apertures of the phosphorus doped silicon oxide layer in a CMOS device prior to contact metalization.
In the manufacture of CMOS devices, a layer of phosphorus doped silicon oxide glass is normally deposited over the active elements of the transistors to protect them from contamination and to insulate them from electrically conductive material which is subsequently deposited to provide contacts for electrodes of the transistors. When contact apertures are etched through the glass layer to expose source, drain and gate regions, however, sharp corners are present at the junction of the aperture walls and the top surface of the glass. If the contact material is deposited on the glass at this point, the thickness thereof is reduced at the sharp corners. This nonuniformity in the conductive material limits its current carrying capacity and presents reliability problems with the integrated circuits. In order to overcome this problem, various techniques are employed to round off the sharp edges of the glass at the contact apertures. One technique is to heat the wafer at an elevated temperature which causes the glass to flow and round the edges of the aperture. This can cause phosphorus ions in the glass to migrate onto the source and drain regions and be baked into the semiconductor material, however, creating a series diode or ohmic contact which impairs or degrades the electrical characteristics of the device. If the wafer sits around for a period of time prior to metalization, the practice is to place the wafer in a weak hydrofluoric acid bath of concentration such as 50:1 for an extended time period such as 40 seconds to remove silicon oxide layers that may build up on exposed surfaces. A short hydrofluoric clean is then employed immediately prior to metalization. Another technique is to use a graded glass which is more heavily doped at the top thereof, i.e., away from the substrate, so as to provide less flow adjacent the semiconductor material. This process is expensive and has met with only moderate success. Another technique is to form tapered walls on the contact apertures with a slope-etch process which undercuts the photoresist. This process is difficult to control and may require a larger surface area of a wafer, which is undesirable.
An object of this invention is an improved method of producing electrical contact areas in an integrated circuit device.